library IEEE;
use IEEE.std_logic_1164.all;

entity testbench_zero_detector_n is
end testbench_zero_detector_n;

architecture test of testbench_zero_detector_n is

	constant N : integer := 8;

	component zero_detector_n
		generic (N : integer);
		port (
			d_i 	: in  std_logic_vector(N-1 downto 0);
			zero_o  : out std_logic
		);
	end component;

	signal d 	: std_logic_vector(N-1 downto 0);
	signal zero : std_logic;

begin

	zero_detector_inst : zero_detector_n
	generic map (
		N => N
	) port map (
		d_i		=> d, 
		zero_o	=> zero
	);

	gen_test : process
	begin
		wait for 100 ns;

		d <= X"05";

		wait for 100 ns;

		d <= X"01";

		wait for 100 ns;

		d <= X"00";

		wait for 100 ns;

		d <= X"80";

		wait for 100 ns;

		d <= X"00";

		wait for 100 ns;

		d <= X"20";

		wait;
	end process;
end test;

